1. Field of the Invention
The invention relates to a microcomputer for driving induction motor, and more particularly, to a microcomputer which outputs a control signal for controlling the driving of induction motor.
2. Description of the Related Art
Conventionally, in a servo system of a three-phase induction motor, a driving control method utilizing a PWM (Pulse Width Modulation) wave, i.e., a so-called carrier driving control method is frequently adopted, because the method can relatively easily attain digital control. In such a driving control method, the period of a carrier is variable, and the time width (duty cycle) of a pulse generated in synchronous with the carrier is controlled, thereby obtaining a control signal. The driving of the three-phase motor is controlled on the basis of the control signal.
FIG. 1 is a block diagram showing a configuration of a conventional microcomputer for driving induction motor, which outputs a control signal for controlling the driving of a three-phase motor M. The conventional microcomputer for driving induction motor mainly consists of four timers 1, 2A, 2B and 2C, a three-phase wave-form generating circuit 3, and a CPU 5 which manages the whole control.
The timer 1 is used for determining the period of a carrier. Specifically, a clock signal CLK is supplied to the timer 1 as a count source. An operation of outputting a high-level pulse of an overflow signal OVF when the count value reaches a predetermined value is repeated, so as to determine the period of the carrier. The timer 1 outputs an interrupt signal INT to the CPU 5 at a rate of one pulse per two pulses of the overflow signal OVF.
The timers 2A, 2B and 2C correspond to three phases U, V and W of the control signal, respectively. Each timer determines the time width of a pulse of the control signal in the corresponding phase which is synchronized with the carrier.
The three-phase wave-form generating circuit 3 generates three phase control signals U, V and W and their inversion control signals #U, #V and #W, in accordance with the outputs of the timers 2A, 2B and 2C. The control signals outputted from the three-phase wave-form generating circuit 3 are supplied to a motor control circuit 3 which is disposed outside the microcomputer, and the driving of the three-phase motor M is controlled by the output of the motor control circuit 3.
The timers 2A, 2B and 2C which respectively correspond to the three phases U, V and W of the control signal have identical configurations. Herein, therefore, the timer 2A for the U phase is exemplarily described.
The timer 2A mainly consists of two timer registers 4A and 4B, a selector 4C, a reload register 4D, and a counter 4E.
The timer registers 4A and 4B store data supplied from the CPU 5. The data supplied from the CPU 5 to the timer registers 4A and 4B are the data for determining the time width of a pulse of the control signal for the U phase. In the following description, such data is referred to as time width data. Either of the time width data stored in the timer register 4A and that stored in the timer register 4B is selected by the selector 4C.
The selector 4C operates at falling timing of the pulse of the overflow signal OVF outputted from the timer 1. At each operation, the selector 4C alternately selects and outputs the time width data stored in the timer register 4A and that stored in the timer register 4B. The time width data selected by the selector 4C is supplied to the reload register 4D and held thereby.
The reload register 4D operates at rising timing of the pulse of the overflow signal OVF outputted from the timer 1, and outputs the held data which is then supplied to the counter 4E.
A trigger terminal TG of the counter 4E receives the overflow signal OVF outputted from the timer 1. The counter 4E regards the rising edge of the high-level pulse of the overflow signal OVF as a trigger, and starts the operation of counting the clock signal CLK supplied as the count source. The count operation of the counter 4E is continued until the count value reaches the data supplied from the reload register 4D. During the count operation, the counter 4E outputs a high-level signal. During the period from the termination of the count operation to the start of the next count operation (the rising timing of the pulse of the overflow signal OVF), the counter 4E outputs a low-level signal. The output of the counter 4E is supplied to the three-phase wave-form generating circuit 3 as an output OUT2A of the timer 2A.
The timers 2B and 2C output their outputs OUT2B and OUT2C and supply them to the three-phase wave-form generating circuit, in the same way as the above-described timer 2A.
Next, the operation of the conventional microcomputer for driving induction motor shown in FIG. 1 will be described.
The microcomputer operates as a whole in the following manner.
The timer 1 generates a high-level pulse of the overflow signal OVF for each overflow of its time count value. The pulse of the overflow signal OVF is supplied to the timers 2A, 2B and 2C. Accordingly, the timers 2A, 2B and 2C start their time count operations for respective predetermined time periods, and output signals OUT2A, OUT2B and OUT2C of pulses which have predetermined time widths and which are synchronized with the carrier, to the three-phase wave-form generating circuit 3. By repeating such the operation, the three-phase wave-form generating circuit 3 generate and output the control signals U, V and W, and #U, #V and #W respectively corresponding to the three phases U, V and W. The three phase control signals U, V and W, and #U, #V and #W outputted from the three-phase wave-form generating circuit 3 are supplied to the motor control circuit 30. The driving of the three-phase motor M is controlled by the output of the motor control circuit 30.
Next, with reference to a timing chart of FIG. 2 showing the states of the signals in various portions, the operations of determining the time widths of the positive phase control signals U, V and W and the negative phase signals #U, #V and #W in the respective three phases will be described by way of an example of the U phase.
It is assumed that the time width data are previously supplied from the CPU 5 and stored in the timer registers 4A and 4B, and the time width data stored in the timer register 4A is loaded to the reload register 4D through the selector 4C and stored therein.
At first, at timing t1 shown in FIG. 2, the timer 1 outputs the overflow signal OVF and the interrupt signal INT. Accordingly, the time width data which has been loaded from the timer register 4A to the reload register 4D is reloaded from the reload register 4D to the counter 4E at the rising timing t1 of the overflow signal OVF. In addition, at the rising timing t1 of the pulse of the overflow signal OVF, the counter 4E starts the count operation, and starts to output a high-level signal. Accordingly, a one-shot signal P1 which, as shown in FIG. 2, is synchronized with the carrier and has a time width corresponding to the time width data stored in the timer register 4A is outputted from the counter 4E to the three-phase wave-form generating circuit 3 as the output signal OUT2A.
At the timing t1, also the interrupt signal INT is outputted from the timer 1 and supplied to the CPU 5. In response to the signal, the CPU 5 calculates the time width data which will be loaded to the timer registers 4A and 4B of the timer 2A at the next time, and also the time width data which will be loaded to the two timer registers respectively included in the other timers 2B and 2C at the next time. In addition, the CPU 5 performs the processing for loading a total of six data to the corresponding six timer registers, before the next overflow signal OVF is inputted.
At falling timing t11 of the pulse of the overflow signal OVF, the selector 4C is activated to perform the switching operation, so that the time width data stored in the timer register 4B is loaded to and held by the reload register 4D.
When the count operation of the counter 4E is terminated at timing t12, in other word, when the count value of the counter 4E reaches the value which is previously reloaded from the reload register 4D, the counter 4E starts to output a low-level signal.
When the timer 1 outputs the next pulse of the overflow signal OVF, the time width data which has already been loaded from the timer register 4B to the reload register 4D is reloaded to the counter 4E at the rising timing t2 of the high-level pulse shown in FIG. 2. At timing t2, the interrupt signal INT is not outputted. The counter 4E starts the count operation at the rising timing t2 of the pulse of the overflow signal OVF, and starts to output a high-level signal. Accordingly, a one-shot signal P2 which, as shown in FIG. 2, is synchronized with the carrier and has a time width corresponding to the time width data stored in the timer register 4B is outputted from the counter 4E to the three-phase wave-form generating circuit 3 as the output signal OUT2A.
At falling timing t21 of the second pulse of the overflow signal OVF, the selector 4C is activated to perform the switching operation, so that the time width data stored in the timer register 4A is transferred to and held by the reload register 4D.
When the count operation of the counter 4E is terminated at timing t22, in other words, when the count value of the counter 4E reaches the value which is previously reloaded from the reload register 4D, the counter 4E starts to output a low-level signal.
At the same time when the next pulse of the overflow signal OVF is outputted, the interrupt signal INT is outputted so that the time width data of the timer registers 4A and 4B are updated to new data.
By repeating such the operation, the CPU 5 sequentially rewrites the values of the time width data in the timer registers 4A and 4B, so as to control the time widths (the pulse widths) of the one-shot signals P1 and P2 which are the output signal OUT2A of the counter 4E.
When these one-shot signals P1 and P2 which are the output OUT2A of the timer 2A are supplied to the three-phase wave-form generating circuit 3, as shown in FIG. 2, the three-phase wave-form generating circuit 3 generates a U-phase control signal U which falls at the falling timing t12 of the one-shot signal P1 and rises at the falling timing t22 of the one-shot signal P2. The three-phase wave-form generating circuit 3 generates also a U-phase inversion control signal #U which rises at the falling timing t12 of the one-shot signal P1 and falls at the falling timing of the one-shot signal P2.
The control signals V and W, and their inversion control signals #V and #W for the V and W phases other than the U phase are also generated in the same way.
On the other hand, in addition to the above-described prior art, a control method for an induction motor in which the driving of a three-phase motor is controlled by a microcomputer using a PWM wave is disclosed in Japanese Patent Application Laid-Open No. 57-78389 (1982), an apparatus for driving an induction motor is disclosed in Japanese Patent Application Laid-Open No. 61-109493 (1986), and an inverter control apparatus is disclosed in Japanese Patent Application Laid-Open No. 60-200773 (1985).
The above-described control by the CPU 5 for determining the time widths of the one-shot signals P1 and P2 necessitates the processing including 12 steps of the following step 1 to step 12:
Step 1: Calculation of time width data to be written into one timer register 4A of the timer 2A for U-phase. PA1 Step 2: Calculation of time width data to be written into the other time register 4B of the timer 2A for U-phase. PA1 Step 3: Calculation of time width data to be written into one timer register of the timer 2B for V-phase. PA1 Step 4: Calculation of time width data to be written into the other timer register of the timer 2B for V-phase. PA1 Step 5: Calculation of time width data to be written into one timer register of the timer 2C for W-phase. PA1 Step 6: Calculation of time width data to be written into the other timer register of the timer 2C for W-phase. PA1 Step 7: Writing of the calculation result to the one timer register 4A of the timer 2A for U-phase. PA1 Step 8: Writing of the calculation result to the other timer register 4B of the timer 2A for U-phase. PA1 Step 9: Writing of the calculation result to the one timer register of the timer 2B for V-phase. PA1 Step 10: Writing of the calculation result to the other timer register of the timer 2B for V-phase. PA1 Step 11: Writing of the calculation result to the one timer register of the timer 2C for W-phase. PA1 Step 12: Writing of the calculation result to the other timer register of the timer 2C for w-phase.
Because the control necessitates the processing of these 12 steps, the load on the CPU 5 is remarkably increased, and there is a fear that there is no margin for performing other processing. In addition, it is necessary for the CPU 5 to complete the processing within the time interval between the reception of the pulse of the interrupt signal INT from the timer 1 and that of the next pulse of the overflow signal OVF from the timer 1. Accordingly, the period of the carrier set by the timer 1, i.e., the period of the overflow of the timer 1 cannot be shorter than the time period required for completing the processing of the 12 steps. Consequently, the frequency of the carrier is limited, so that there arises a problem in that it is difficult to more smoothly control the revolution of the three-phase motor.
On the other hand, in the control method for an induction motor disclosed in Japanese Patent Application Laid Open No. 57-78389 (1982), a current instruction having an accurate sinusoidal waveform without any distortion even in higher frequencies is generated. In the apparatus for driving an induction motor disclosed in Japanese Patent Application Laid-Open No. 61-109493 (1986), the control which is matched with a DC motor control can be applied to a general-purpose AC motor. In the inverter control apparatus disclosed in Japanese Patent Application Laid-Open No. 60-200773 (1985), the capacity of the storage unit which stores combinations of ON-OFF states of a plurality of switching elements constituting a three-phase bridge can be reduced. Accordingly, none of the above-described inventions have been conducted so as to reduce the load on the CPU and increase the frequency of the carrier in the control of the driving of an induction motor.
Hence, in the timing chart of FIG. 2, at the timing of t1, that is, the timing at which the timer 1 generates the interrupt signal INT, the CPU 5 performs an operation for obtaining data corresponding to the period (a) of the output signal OUT2A of the timer 2A, and stores the operation result into the timer register 4A of the timer 2A. Next, the CPU 5 performs an operation for obtaining data corresponding to the period (c) of the output signal OUT2A of the timer 2A, and stores the operation result into the timer register 4B of the timer 2A.
Here, low level period (c+cc) of the wave-form of the U phase of the control signal, that is, high level period of the wave-form of the #U phase which is the inverted phase of the U phase is determined by following equation. EQU period (b)-period (a)+period (c)
In driving control of the general three-phase motor, following equation is established. EQU period (b)-period (a)=period (c)
In addition, because the period (b) which is the cycle of the carrier is constant, when the value (which corresponds to the period (a)) to be stored in the timer register 4A is determined, the value (which corresponds to the period (c)) to be stored in the timer register 4B is determined uniquely by the subtraction of above equation.